The present invention relates to a semiconductor device with a MISFET (Metal Insulator Semiconductor Field Effect Transistor) isolated by a shallow trench isolation (STI) structure and, more particularly, to a semiconductor device with a wide-channel MISFET having a reverse narrow channel effect substantially the same as that of a narrow-channel MISFET.
As the integration degree of semiconductor devices increases, the isolation portion of a MISFET as the main element constituting the integrated circuit of a semiconductor device must also be micropatterned. To isolate a MISFET, shallow trench isolation is employed in place of an isolation structure, e.g., LOCOS (LOCal Oxidation of Silicon), which is difficult to micropattern. Shallow trench isolation is employed because of two main reasons. The first reason is that when the isolation width becomes almost 0.35 xcexcm or less, in a LOCOS structure, the isolation breakdown voltage decreases rapidly. The second reason is a decrease in element region occurring when an oxide film bites in it, which is called a bird""s beak of LOCOS. A scheme that solves these problems to decrease the pitch of elements to be arranged is shallow trench isolation. This is indispensable in high integration of elements.
In a semiconductor device integrated circuit, a plurality of MISFETs with various channel widths different from each other are formed on a single substrate. For example, a narrow-channel MISFET and a wide-channel MISFET are used as elements constituting a static random access memory and a power circuit, respectively, of one semiconductor device, and are mixedly formed on one substrate.
FIGS. 7 and 8 show a conventional semiconductor device with a plurality of MISFETs isolated by shallow trench isolation and having channel widths different from each other.
As shown in FIGS. 7 and 8, a conventional semiconductor device 60 has, on a silicon substrate 62, three narrow-channel MISFETs 66 each with a small channel width W1 and a wide-channel MISFET 68 with a large channel width W2 respectively formed in element formation regions defined by shallow trench isolation regions 64.
The narrow-channel MISFETs 66 and wide-channel MISFET 68 respectively have gate electrodes 72 and 74 through gate insulating films 70. Each narrow-channel MISFET 66 has a source electrode 76 and drain electrode 78 respectively at its two channel ends. The wide-channel MISFET 68 has a source electrode 80 and drain electrode 82 respectively at its two channel ends.
The conventional semiconductor device described above has the following problems. FIG. 10 shows the gate voltage to drain current characteristics of MISFETs with 0.2-, 1-, and 10-xcexcm channel widths which serve as conductor paths. It is apparent from FIG. 10 that the gate voltage to drain current characteristics of the MISFETs with 1- and 10-xcexcm channel widths form nonlinear curves with steps. In other words, hump characteristics appear in these characteristics. The subthreshold regions of MISFETs with the 1- and 10-xcexcm channel widths and exhibiting the hump characteristics have the same characteristics as those of the MISFET with the 0.2-xcexcm channel width where no hump characteristic is observed.
In order to explain these phenomena, the channel of a MISFET will be analyzed by dividing it into a channel side edge portion along the shallow trench isolation region and a channel planar portion between two channel side edge portions when seen in the direction of channel width. Note that the channel side edge portion is rounded with a predetermined radius of curvature during a MISFET manufacturing process.
In a wide-channel MISFET with a shallow trench isolation structure, when a voltage is applied to the gate electrode, a gate electric field generated by the applied voltage is locally concentrated at the channel side edge portion crossing the gate electrode. Even when the same gate voltage is applied, the gate electric field becomes higher at this portion than at the channel planar portion, and the threshold voltage of the channel side edge portion becomes lower than the threshold voltage of the channel planar portion. Therefore, an inversion layer is formed in the channel side edge portion before in the channel planar portion to render an ON state, so a channel drain starts to flow undesirably.
As a result, the channel side edge portion of the MISFET where the threshold voltage is low and the channel planar portion of the MISFET where the threshold voltage is high exist in the form of parallel connection. For this reason, in a wide-channel MISFET, e.g., one with a channel width of 10 xcexcm, a hump characteristic curve indicated by a solid line in FIG. 10 appears where that indicated by a broken line is to be obtained ideally. The hump characteristics are represented by two curve portions sandwiching a characteristic change point.
In a narrow-channel MISFET, e.g., one with a channel width of 0.2 xcexcm, the channel planar portion has a width almost equal to the radius of curvature of the channel side edge portion. Thus, the gate electric field becomes almost equal between the channel side edge portion and the channel planar portion. In this case, the threshold voltage of the channel planar portion becomes equal to that of the drain current flowing through the channel side edge portion, inversion layers are formed in the channel side edge portion and channel planar portion simultaneously, and drain current starts to flow there. Therefore, the hump characteristics are not observed.
Appearance of the hump characteristics described in the above manner means that a subthreshold coefficient degrades in a wide-channel MISFET. In other words, the switching characteristics of the MISFET degrade. Due to the hump characteristics, upon application of a gate voltage equal to or lower than the threshold voltage, even when the gate voltage is kept unchanged, a subthreshold current larger than the ideal subthreshold characteristics by one or more orders of magnitudes flows. Therefore, if the MISFET is OFF, the power consumption increases.
Another problem arises as follows. When the channel width of the MISFET becomes 2 xcexcm or less, the threshold voltage of the MISFET decreases greatly depending on the channel width, that is, a phenomenon called a reverse narrow channel effect occurs.
FIG. 9 shows the channel width dependence of the threshold voltage, i.e., so-called narrow channel characteristics, that occurs when the channels of the MISFETs are doped with an impurity of the same concentration. The reverse narrow channel effect appears in these narrow channel characteristics. As shown in FIG. 9, with the channel width of 2 xcexcm or less, the threshold voltage varies depending on the channel width due to the reverse narrow channel effect. Therefore, in the semiconductor device described above with the wide- and narrow-channel MISFETs on the same substrate, the threshold voltage of the wide-channel MISFET and that of the narrow-channel MISFET differ from each other.
According to xe2x80x9cTED Control Technology for Suppression of Reverse Narrow Channel Effect in 0.1 xcexcm MOS Devicexe2x80x9d, Technical Digest of International Electron Device Meeting 1997, pp. 227-230, December 1997 (reference 1), during the manufacturing process for a MISFET with shallow trench isolation, transient enhanced diffusion causes redistribution of the channel impurity in the channel side edge portion. Hence, in a MISFET with a small channel width, the impurity concentration decreases over the entire channel when compared to that in a wide-channel MISFET.
When a MISFET with these characteristics is used in an integrated circuit, the following problems arise. For example, a static RAM with a CMOS cell structure is sometimes designed with a channel width of 0.3 xcexcm or less to achieve a high integration degree. At this time, if the concentration of the channel impurity is set to match the threshold voltage of a wide-channel MISFET existing on the same substrate, sufficient cutoff is disabled because of a decrease in threshold voltage described above.
Consequently, a short circuit current, in other words, a subthreshold current, flows in the CMOS circuit to increase the power consumption, thereby degrading the circuit performance. In an integrated circuit where MISFETs with variously different channel widths are present, the timings of signals generated by respective signal circuits that make up the integrated circuit do not coincide with each other to cause clock skew, thus hindering the circuit operation. In this manner, the reverse narrow channel effect adversely affects the integrated circuit seriously.
When silicon oxide is used to form an insulator that fills an isolation trench to constitute the shallow trench isolation region 64 (FIGS. 7 and 8), the silicon oxide which fills the isolation trench is etched with hydrofluoric acid in a process during the integrated circuit manufacture. Hence, the upper surface of the shallow trench isolation region becomes lower than the intermediate channel portion of the MISFET, thus forming a gate electrode to surround the channel side edge portion. As a result, the electric field formed upon application of the gate voltage to the gate electrode is further enhanced to decrease the threshold voltage more greatly.
xe2x80x9cA Robust 0.15 xcexcm CMOS Technology with CoSi2 Salicide and Shallow Trench Isolationxe2x80x9d, 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 125-126, June 1997 (reference 2) proposes an attempt to suppress the reverse narrow channel effect phenomenon by ion-implanting an impurity to the trench side wall.
According to inference from reference 2, as shown in FIG. 11A, a silicon oxide film 81 and silicon nitride film 82 are sequentially formed on a silicon substrate 62. The silicon oxide film 81 and silicon nitride film 82 are etched by using a photoresist 83, the element region of which has been patterned by lithography, to form an etching mask for silicon nitride film 82. Subsequently, as shown in FIG. 11B, the silicon substrate 62 is etched to form an isolation trench 84 by using the etching mask of the silicon nitride film 82, and an impurity is introduced to the side wall of the isolation trench 84.
As shown in FIG. 11C, an insulating film 85 is formed on the entire surface of the silicon substrate 62, thereby burying the insulating film 85 in the isolation trench 84. As shown in FIG. 11D, the insulating film 85 is planarized to form a shallow trench isolation region 64. After that, the silicon nitride film 82 is removed, and an impurity for determining the threshold voltage is introduced to the channel portion of the MISFET. Then, as shown in FIG. 11E, a gate insulating film 70 and gate electrode 74 are formed, thereby forming the MISFET.
To suppress the problem caused by the reverse narrow channel effect in accordance with the method described in reference 2, a compensation step such as an ion implantation step of implanting an impurity for adjusting the threshold voltage is required, as shown in FIG. 11B. This complicates the process to lead to an increase in the manufacturing cost.
It is an object of the present invention to provide a semiconductor device in which the threshold voltage does not vary depending on the size of the channel width.
It is another object of the present invention to provide a semiconductor device with good, linear gate voltage to drain current characteristics.
It is still another object of the present invention to provide a semiconductor device in which the number of steps is decreased to decrease the manufacturing cost.
In order to achieve the above objects, according to the present invention, there is provided a semiconductor device comprising a plurality of shallow trench isolation bands formed in a band-like shape within an element formation region defined by a shallow trench isolation region, a plurality of channels isolated from each other by the shallow trench isolation bands and extending parallel to each other, a common source region/electrode formed at one end of each of the channels, a common drain region/electrode formed at the other end of each of the channels, and a common gate electrode formed on the channels across the shallow trench isolation bands.